As the explosion of electronic devices such as televisions, computers (i.e., anything that computes), monitors, mobile phones, personal digital assistants, handheld devices, etc. continue to push the technological envelope with respect to their ability to perform tasks quicker and better than each previous generation, size and power considerations remain important to both the consumer and the circuit designer. The two considerations often go hand-in-hand as a decrease in size of a handheld device, for instance, may require a battery source that is limited in physical size and therefore may require more frequent charging or replacement when compared to a similarly constructed battery having similar electrical properties but being larger in size. Others having ordinary skill in the art will also appreciate other relationships (e.g., between size and power) of integrated circuit components.
It is well known that integrated circuits supplied with more than one voltage grid are said to have more than one voltage domain, wherein each voltage domain is associated with the voltage level provided by its associated voltage grid. It is further well known to selectively power up or power down a voltage domain by selectively providing voltage to the voltage domain's voltage grid. Accordingly, voltage domains may also be referred to as power domains. It is also well known that an integrated circuit's multiple voltage domains may have voltage levels at the same or different values.
FIG. 1 illustrates a block diagram of one example of an integrated circuit 100 that conceptually shows features relevant to the present disclosure. The integrated circuit 100 includes three voltage domains: a first voltage domain 102, a second voltage domain 104 and a third voltage domain 106. The first voltage domain 102 and the third voltage domain 106 are associated with the positive voltage supply grid VDD1 108 while the second voltage domain 104 is associated with another voltage supply grid VDD2 109. For purposes of this example, the another voltage supply grid VDD2 109 is a selectably on voltage supply grid VDD2 that has a voltage level at or substantially at the voltage level associated with the positive voltage supply grid VDD1 108 when the selectably on voltage supply grid VDD2 109 is on. One or more switching cells (not specifically shown) having switch logic (e.g., a PMOS transistor) associated therewith are coupled between the positive voltage supply grid VDD1 108 and the selectably on voltage supply grid VDD2 109 to control whether the selectably on voltage supply grid VDD2 109 is on or off. It is contemplated that the another voltage supply grid VDD2 109 may be any other voltage grid that is always on (as compared to being selectably on) and/or that is at a different voltage level than the voltage level associated with the positive voltage supply grid VDD1 108. As used herein, the term switch logic is synonymous with the term switch and refers to any suitable integrated circuit component(s) capable of performing a switching function as known in the art.
One having ordinary skill in the art recognizes that integrated circuits include standard cells that include logic designed, programmed or programmable to perform a particular circuit function. As is recognized “logic” may include any suitable combination of integrated circuit components (e.g., transistors). It is further recognized that standard cells in an integrated circuit are generally found in the lower layers of an integrated circuit (e.g., in the substrate region and in the lower metal layers). Returning to FIG. 1, standard cells (not specifically shown) within the first voltage domain 102 of the integrated circuit 100 are coupled to the positive voltage supply grid VDD1 108. Standard cells (not specifically shown) in the second voltage domain 104 of the integrated circuit 100 are coupled to the selectably on voltage supply grid VDD2 109. Similarly, standard cells (not specifically shown) in the third voltage domain 106 of the integrated circuit 100 are coupled to the positive voltage supply grid VDD1 108.
The positive voltage supply grid VDD1 108 powers the standard cells in the first and third voltage domains 102 and 106 of the integrated circuit 100 by supplying the positive voltage level associated with the positive voltage supply grid VDD1 108 to each of the standard cells. Similarly, the selectably on voltage supply grid VDD2 109 of the second voltage domain 104 of the integrated circuit 100 powers the standard cells in the second voltage domain 104 of the integrated circuit 100. Because the selectably on voltage supply grid VDD2 109 is a voltage supply grid that is capable of being powered up and powered down, the standard cells in the second voltage domain 104 are also capable of being selectively powered up and powered down.
It is further recognized that additional cell types besides the standard cell as introduced above are used in integrated circuits to perform certain functions. For example, the switching cell (also introduced above) and the buffer cell (described in further detail below) are additional types of cells used in an integrated circuit.
Implicit in the above discussion is the need and use of a negative voltage supply grid. For example, many integrated circuit components require one or more terminals coupled to ground or a sufficiently low voltage source or supply. FIG. 1 illustrates such a negative voltage supply grid as negative voltage supply grid VSS 110. Generally, each of the voltage supply grids (positive and negative) in an integrated circuit are associated with the upper-most metal layers, are arranged in a grid (as further discussed below) and are coupled to cells and/or power-ground rails (associated with the middle or lower layers of the integrated circuit) using a piece of metal called a via stack. The via stack provides electrical connectivity between the associated voltage supply grid and to the cells of the integrated circuit. As is known, power-ground rails (vertical or horizontal) are used to carry voltage from cell to cell without having to tap the voltage supply grid using via stacks for each cell. Each time the term “via stack” is used throughout this disclosure, it is recognized and contemplated that any other suitable electrical conduit or wire is and may be capable of similarly providing this electrical connectivity.
The integrated circuit 100 of FIG. 1 illustrates a transmitting standard cell 112 associated with or located in the first voltage domain 102 and a receiving standard cell 114 associated with or located in the third voltage domain 106. The transmitting standard cell 112 is a standard cell that is capable of transmitting a feed-through signal 113 through the second voltage domain VDD2 104 of the integrated circuit 100 to the third voltage domain 106 of the integrated circuit 100 to, for example, the receiving standard cell 114. The feed-through signal 113 is so named because it is fed through another voltage domain (e.g., voltage domain 102). The feed-through signal 113 has a logic one voltage level at or substantially at the voltage level of the positive voltage supply grid VDD1 108 and represents any suitable information for transmission from one standard cell to another standard cell in the integrated circuit 100. The information carried on feed-through signal 113 is carried on a metal path or any other suitable transmission conduit or wire capable of electrical connectivity (not specifically shown). Although FIG. 1 shows a specific example of feed-through signal 113, it is known that feed-through signals may be fed through any number of different voltage domains and may be received by any number of suitable standard cells.
It is recognized that the due to physical parameters such as length of the transmission path from the transmitting standard cell 112 to the receiving standard cell 114, etc., the signal strength of the feed-through signal 113 may be attenuated or otherwise adversely affected by noise and/or other electromagnetic effects if it is not buffered up to or substantially close to the voltage level of the feed-through signal's 113 logic one voltage level. By buffering the feed-through signal 113, the information conveyed on the feed-through signal 113 may be more reliable than it would be otherwise. It is recognized that one or more buffers in any suitable cell(s) (e.g., an independent buffer cell or a switching cell that includes buffer) may be coupled between the transmitting standard cell 112 and the receiving standard cell 114 to buffer the feed-through signal 113. As used herein, the term buffer is synonymous with the term buffer logic and refers to any suitable combination of integrated circuit components capable of performing buffering functions as known in the art.
It is generally desirable to buffer feed-through signals 113 within the second voltage domain 104 as it is at this location where the signal strength often needs to be improved for accurate transmission of information to the receiving standard cell (e.g., receiving standard cell 114). Using the example of FIG. 1, this poses a problem because the second voltage domain 104 is capable of being selectively turned on and off. If a buffer is implemented in the second voltage domain 104 such that it is powered by the selectably on voltage power grid VDD2 109, the buffer may not be operational (i.e., turned on) when needed.
To address this problem, it is known to couple a buffer such as buffer 116 to the positive voltage supply grid VDD1 108 as shown in FIG. 1. The implementation details regarding the coupling of the positive voltage supply grid VDD1 108 (associated with the first voltage domain 102) to buffer 116 associated with or located in the second voltage domain 104 is discussed below. As is known, buffers may be implemented in a stand-alone cell called a buffer cell or may be implemented in a switching cell. However, prior art solutions either limited the location of buffers to specific locations and thereby fixed the number of available buffers in the second voltage domain 104 or required the use of or dependency upon at least one switching cell as discussed below. Following these prior art methodologies was costly as it limited the locations where circuit designers placed buffers and resulted in limiting the number of feed-through signals that could be fed through and buffered in a second voltage domain like second voltage domain 104 of integrated circuit 100.
FIG. 2 illustrates a schematic block diagram of one example of a switching cell 200 in accordance with the prior art. Switching cell 200 includes switching logic 202 without a buffer. Switching logic 202 may be any suitable logic capable of providing a switching function. In this example, switching logic 202 is implemented using a PMOS transistor. Switching logic 202 is coupled between the positive voltage supply grid VDD1 108 and the selectably on voltage supply grid VDD2 109. Switching logic 202 receives a sleepin signal 204 from any suitable logic, and based on the sleepin signal 204, switching logic 202 is capable of turning on or off the selectably on voltage supply grid VDD2 109. In other words, sleepin signal 204 is any suitable signal, information or data (e.g., but not limited to voltage levels) that represents what state (i.e., on or off) within which switching logic 202 should operate. In one embodiment, when the sleepin signal 204 is equivalent to a logic 0, switching logic 202 goes “to sleep”. The logic that provides the sleepin signal 204 may be from any suitable source such as a processing unit (e.g., a central processing unit(s)) in a computing device, or any other functional cell on the same or different integrated circuit in which the switching cell is located.
FIG. 3 illustrates a schematic block diagram of another example of a switching cell 300 in accordance with the prior art. Switching cell 300 includes switching logic 202 and buffer logic 116. Buffer logic 116 is coupled between the positive voltage supply grid VDD1 108 and the negative voltage supply grid VSS 110 and operates the same as provided above with reference to FIG. 1. Switching logic 202 operates as described above with respect to FIG. 2.
FIG. 4 illustrates a schematic block diagram of one example of a buffer cell 400 in accordance with the prior art. Buffer cell 400 implements buffer logic 116 as two inverters I 502, 504 coupled in series and is coupled between the positive voltage supply grid VDD1 108 and the negative voltage supply grid VSS 110. FIG. 5 illustrates a more detailed schematic block diagram of the buffer cell 400 of FIG. 4 and specifically shows each inverter I 502, 504 implemented using CMOS transistors as is known in the art.
FIG. 6 illustrates a top plan view 600 of a portion of integrated circuit 100 of FIG. 1 in accordance with the prior art. FIG. 6 illustrates positive voltage supply grid VDD1 108 in relative relation to negative voltage supply grid VSS 110 and selectably on voltage supply grid VDD2 109. In this illustration, positive voltage supply grid VDD1 108 includes a plurality of metals that are substantially parallel to each other in a first direction (e.g., in a substantially vertical direction) in addition to a plurality of metals that are substantially parallel to one another in an orthogonal direction with respect to the aforementioned plurality of illustrated metals in the first direction (e.g., in a substantially horizontal direction). One having ordinary skill in the art will recognize that each of the negative voltage supply grid VSS 110 and the selectively on voltage supply grid VDD2 109 is illustrated in a similar manner. As further illustrated, the selectably on voltage supply grid VDD2 109 overlaps a portion of both the positive voltage supply grid VDD1 108 and the negative voltage supply grid VSS 110. In FIG. 6, this area of overlap is indicated by area 104 and indicates the location of the second voltage domain 104 of the integrated circuit 100 of FIG. 1. The area of non-overlap indicates the location of the first voltage domain 102. The metals associated with the positive and negative voltage supply grids VDD1 108 and VSS 110 are illustrated larger than the metals associated with the selectively on positive voltage supply grid VDD2 109 for purposes of clarity and to further illustrate that these pluralities of metals are typically (but not necessarily) of a larger size than the metals associated with the selectably on voltage supply grid VDD2 109 to avoid adverse switching effects such as a large IR drop.
In prior art cell layouts where the substantially horizontal members of each of the power supply grids VDD1 108, VDD2 109 and VSS 110 are primarily used to distribute the associated voltage level of the grid throughout integrated circuit 100, the substantially vertical members of each power supply grid are primarily used to provide electrical connectivity to cells within corresponding and respective voltage domains. According, the substantially horizontal members are typically located in a higher metal layer than the corresponding substantially vertical members of the power supply grids. The opposite is true for prior art cell layouts that use substantially horizontal members for providing electrical connectivity to cells with corresponding and respective voltage domains and use substantially vertical members for distribution throughout the integrated circuits. Via stacks are used to couple vertical and horizontal members of like voltage supply grids.
In prior art cell layouts where the substantially horizontal members of each of the voltage supply grids VDD1 108, VDD2 109 and VSS 110 are primarily used to distribute the associated voltage level of the grid throughout the integrated circuit 100, such as that shown in FIG. 6, switching cells without buffers 200 and switching cells with buffers 300 are generally placed or otherwise located beneath the substantially vertical metals highlighted by areas 606 and coupled between the substantially vertical members of positive voltage supply grid VDD1 108 and the selectably on voltage supply grid VDD2 109 using via stacks. It is further recognized that the ideal location for placement of a switching cell with or without a buffer 200, 300 is below the intersection of the substantially vertical members of both the positive voltage supply grid VDD1 108 and the selectably on voltage supply grid VSS 109 with the substantially horizontal members of the same grids as indicated by the area labeled with reference numeral 608. This location is considered ideal to the extent that the distance from the substantially horizontal positive voltage supply grid VDD1 108 (for distribution) to the substantially vertical positive voltage supply grid VDD1 108 (for cells) to the substantially vertical selectably on voltage supply grid VDD2 109 (for cells) to the substantially horizontal selectably on voltage supply grid VDD2 109 (for distribution) is minimized.
A first prior art solution to adding buffers to the layout described above placed a switching cell having buffer logic 300 in one or more consecutive rows of the integrated circuit layout along the columns highlighted by areas 606 of FIG. 6. Accordingly, this prior art solution formed a column of switching cells with buffer logic 300 substantially along or substantially beneath the substantially vertical members of the positive and selectably on voltage supply grids VDD1 108 and VDD2 109 (“in the columns 606”). The space (identified by reference numeral 609) between each column 606 of switching cells is filed with other cells, namely standard cells associated with or located in the second voltage domain 104. In this solution, numerous via stacks were used to tap the appropriate voltage supply grid (e.g., VDD1 for switching cells 300 and VDD2 for standard cells) and vertical power-ground rails were used to couple one or more adjacent cells vertically when said adjacent cells are not coupled to said associated voltage supply grid. Although this was advantageous to the extent that it provided buffers for feed-through signals in the second voltage domain 104 of the integrated circuit 100, it limited the number of feed-through signals that could be passed through a particular area to the number of available rows as the only buffers available were located in switching cells 300.
A second prior art solution to adding buffers to the layout described above recognized that switching logic was not needed in every row along columns 606. In place of certain switching cells with buffer logic 300, this solution placed buffer cells 400 in the columns 606. Similar to the first solution, the spaces 609 in between columns 606 is filed with other cells, namely standard cells associated with or located in the second voltage domain 104 and all cells are coupled vertically to the respective voltage supply grid. While this second solution was an improvement over the first solution in that it offered a savings in area (due to the replacement of switching cells with buffer logic 300 with buffer cells 400), the solution retained a fixed number of feed-though buffers 116 and presented circuit designers with the possibility of running out of buffers in high congestion areas of feed-through signals.
A third prior art solution to adding buffers to the layout described above required the use of pairs of switching cells and created an area for the placement of buffers therebetween. For example, a switching cell (with or without buffer logic 200, 300) is placed in a row of the integrated circuit layout in a first column 606 and a corresponding switching cell of the pair of switching cells is placed in a second column 606 in the same row of the integrated circuit layout. It is recognized that the adjectives “first” and “second” are used to merely distinguish columns of columns 606. For the space 609 in between corresponding pairs of switching cells (i.e., the space along the same row), a horizontal power-ground rail at the voltage level of the positive voltage supply grid VDD1 108 is placed to supply buffer cells 400 and other cells that do not require the selectively on voltage supply grid VDD2. In other words, each pair of switching cells forms a boundary using a first switching cell of the pair of switching cells as a left-most boundary and using a second switching cell of the pair of switching cells as a right-most boundary. Therebetween, buffer cells 400 are located. This solution, however, does not permit the placement of standard cells associated with the selectably on voltage supply grid VDD2 in the space and corresponding rows that have a pair of switching cells in columns 606. In space and rows that do not have pairs of switching cells in columns 606, any type of standard cell (or other cell) may be placed as recognized by those in the art. Although this solution allowed for the expansion of buffer cells 400 into rows, a buffer cell 400 could only be placed in a row of an integrated circuit layout also having a pair of switching cells in that same row to selectively switch on and off the selectably on power supply voltage grid VDD2 109. In other words, buffers in this solution are dependent on switching cells 200, 300. Thus, this solution also limited the number of buffers available in an integrated circuit by the number of switching cells present and the number of buffers located in the space and corresponding row between pairs of switching cells. The solution also wasted space by not permitting the placement of standard cells in the space and corresponding row between pairs of switching cells.
Accordingly, a need exists for an integrated circuit having buffer cells located in more convenient and numerous locations so that more efficient buffering of feed-through signals may occur. A need further exits for such an integrated circuit having these advantages while also having a grid arrangement of voltage supply grids.